1. Field of the Invention
The present invention relates to a poly-Si thin film transistor (“TFT”) and an organic light-emitting display having the same.
2. Description of the Related Art
Polycrystalline silicon (“p-Si”) has higher electron mobility than that of amorphous silicon (“a-Si”) and has good optical stability. P-Si has been widely used in a variety of fields, and in particular, in thin film transistors (“TFTs”) or memory devices. P-Si TFTs have been used as switching devices in display devices, for example. Display devices using an active device such as a TFT include TFT liquid crystal displays (“LCDs”) and TFT organic light-emitting displays (“OLEDs”).
TFT LCDs or TFT OLEDs have a structure in which pixels are arranged in the form of an X-Y matrix, and a TFT is disposed in each pixel. The performance of LCDs and OLEDs in which a plurality of TFTs are arranged largely depends on electrical characteristics of the TFT. One of the most important aspects to the functionality of a TFT is the electron mobility of an Si active layer. Crystallization is essential to improve the electron mobility of the Si active layer. U.S. Pat. No. 6,322,625 discloses a method of fabricating silicon crystal with excellent electron mobility characteristics. The field of study of silicon crystallization has been rapidly developed so that a crystalline structure approaching single crystallization, or the state where the crystal lattice of a sample of the crystal is continuous and unbroken to the edges of the sample, can be obtained.
One of the disadvantages of a p-Si TFT includes a high rate of current leakage through the TFT when an off signal is sent to the gate terminal thereof. In the p-Si TFT, it is well known that leakage of a current occurs by grain boundary traps in a depletion region of a drain (see Ferry G. Fossum, et al., IEEE Trans. Electron Devices, Vol. ED-32, pp. 1878-1884, 1985).
An offset structure has been proposed to more effectively reduce a leakage current (see M. Rodder et al., IEEE Electron Device Letters, Vol. EDL-6, No. 11, November 1985). An offset region is a lightly doped drain (“LDD”) and is disposed between a channel and a gate or between the channel and a drain, respectively. The LDD lowers an electric field of the drain and reduces field emission caused by a gate voltage and a drain voltage. However, in order to form the offset structure, a local differential doping process using an additional mask is required. In order to successfully perform differential doping in an offset region using the mask, the mask should be precisely aligned on the substrate. However, since an additional mask is used in the above method, the doping process becomes more complicated, yield is reduced and productivity is lowered.
A variety of methods of reducing a reverse leakage current using an LDD are well known. For example, a large gate can reduce a leakage current. However, the size of a light-emitting region within a pixel is of a limited area and a larger gate inevitably reduces that area and therefore the luminous efficiency of a device using large gates is lowered. Alternative methods of reducing the leakage current such as fabricating a dual gate TFT are complicated and manufacturing costs thereof are high. In an OLED, although reduction in a leakage current using an additional circuit in each switching TFT of a pixel is possible, the additional circuit includes an additional device such as a TFT, thus increasing manufacturing costs greatly.